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Basically, if some part of your program satisfies the following conditions, then that part can rightfully be considered lock-free. Shared mutexes are ruled out trivially, because as soon as one thread obtains the mutex, your worst enemy could simply never schedule that thread again.
As an exercise for the reader, consider how two threads could be scheduled in a way such that neither thread exits the loop.
Typically, we identify a specific set of lock-free operations out of the whole codebase. For example, in a lock-free queue, there might be a handful of lock-free operations such as push, pop, perhaps isEmpty, and so on.
- kernel: lockless wake-queues
- An Introduction to Lock-Free Programming
It is algorithmically impossible for the system to lock up during those operations. One important consequence of lock-free programming is that if you suspend a single thread, it will never prevent other threads from making progress, as a group, through their own lock-free operations. This hints at the value of lock-free programming when writing interrupt handlers and real-time systems, where certain tasks must complete within a certain time limit, no matter what state the rest of the program is in.
Operations that are designed to block do not disqualify the algorithm. The remaining codepaths can still be considered lock-free. Lock-Free Programming Techniques It turns out that when you attempt to satisfy the non-blocking condition of lock-free programming, a whole family of techniques fall out: This is where things quickly become diabolical.
So how do these techniques relate to one another?
Atomic Read-Modify-Write Operations Atomic operations are ones which manipulate memory in a way that appears indivisible: No thread can observe the operation half-complete. On modern processors, lots of operations are already atomic.
For example, aligned reads and writes of simple types are usually atomic. Read-modify-write RMW operations go a step further, allowing you to perform more complex transactions atomically. You can call std:: The common RMW operations are usually sufficient. As illustrated by the flowchart, atomic RMWs are a necessary part of lock-free programming even on single-processor systems.
Without atomicity, a thread could be interrupted halfway through the transaction, possibly leading to an inconsistent state. Often, programmers perform compare-and-swap in a loop to repeatedly attempt a transaction. Despite these problems, synchronization primitives, such as critical sections, are generally the best way of coordinating multiple threads.
If the synchronization primitives are too slow, the best solution is usually to use them less frequently. However, for those who can afford the extra complexity, another option is lockless programming.
Lockless Programming Considerations for Xbox 360 and Microsoft Windows
Lockless Programming Lockless programming, as the name suggests, is a family of techniques for safely manipulating shared data without using locks. There are lockless algorithms available for passing messages, sharing lists and queues of data, and other tasks.
When doing lockless programming, there are two challenges that you must deal with: Non-Atomic Operations An atomic operation is one that is indivisible—one where other threads are guaranteed to never see the operation when it is half done. Atomic operations are important for lockless programming, because without them, other threads might see half-written values, or otherwise inconsistent state.
On all modern processors, you can assume that reads and writes of naturally aligned native types are atomic. As long as the memory bus is at least as wide as the type being read or written, the CPU reads and writes these types in a single bus transaction, making it impossible for other threads to see them in a half-completed state.
On x86 and x64 there, is no guarantee that reads and writes larger than eight bytes are atomic. Reads and writes of types that are not naturally aligned—for instance, writing DWORDs that cross four-byte boundaries—are not guaranteed to be atomic.
The CPU may have to do these reads and writes as multiple bus transactions, which could allow another thread to modify or see the data in the middle of the read or write. Composite operations, such as the read-modify-write sequence that occurs when you increment a shared variable, are not atomic. On Xboxthese operations are implemented as multiple instructions lwz, addi, and stwand the thread could be swapped out partway through the sequence. On x86 and x64, there is a single instruction inc that can be used to increment a variable in memory.
If you use this instruction, incrementing a variable is atomic on single-processor systems, but it is still not atomic on multi-processor systems. Making inc atomic on x and xbased multi-processor systems requires using the lock prefix, which prevents another processor from doing its own read-modify-write sequence between the read and the write of the inc instruction.
The following code shows some examples: Naturally atomic operations Locks to wrap composite operations Operating system functions that implement atomic versions of popular composite operations Incrementing a variable is not an atomic operation, and incrementing may lead to data corruption if executed on multiple threads.
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These are the InterlockedXxx family of functions. If all modifications of the shared variable use these functions, the modifications will be thread safe. Reads and writes do not always happen in the order that you have written them in your code, and this can lead to very confusing problems. In many multi-threaded algorithms, a thread writes some data and then writes to a flag that tells other threads that the data is ready.
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This is known as a write-release. If the writes are reordered, other threads may see that the flag is set before they can see the written data. Similarly, in many cases, a thread reads from a flag and then reads some shared data if the flag says that the thread has acquired access to the shared data. This is known as a read-acquire.
If reads are reordered, then the data may be read from shared storage before the flag, and the values seen might not be up to date. Reordering of reads and writes can be done both by the compiler and by the processor. Compilers and processors have done this reordering for years, but on single-processor machines it was less of an issue.
This is because CPU rearrangement of reads and writes is invisible on single-processor machines for non-device driver code that is not part of a device driverand compiler rearrangement of reads and writes is less likely to cause problems on single-processor machines. If the compiler or the CPU rearranges the writes shown in the following code, another thread may see that the alive flag is set while still seeing the old values for x or y.
Similar rearrangement can happen when reading. In this code, one thread adds a new entry to the sprite array: This rearranging is never visible to single-threaded non-driver code, but it can cause problems in multi-threaded code. Xbox While the Xbox CPU does not reorder instructions, it does rearrange write operations, which complete after the instructions themselves. This rearranging of writes is specifically allowed by the PowerPC memory model. Writes on Xbox do not go directly to the L2 cache.
Instead, in order to improve L2 cache write bandwidth, they go through store queues and then to store-gather buffers.